1. Field of the Invention
The present invention generally relates to the packaging of semiconductor chips. In particular, the present invention relates to a structure and a method of manufacturing a Pb-free, Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure that reduces chip-level back-end-of-line (BEOL) cracking. More particularly, the present invention relates to electroplating of Ni on an exposed edge of a metal seed layer of the BLM structure to reduce undercut of the BLM structure.
2. Description of Related Art
In a Pb-free C4 methodology, formation of solder bumps is accomplished by forming an under bump or Ball Limiting Metallurgy (BLM) structure, comprising a stack of metal layers that are connected by an electrically conductive via to an underlying final metallization layer of a semiconductor chip, and by subsequently forming an overlying solder bump on the BLM structure. Ideally, the BLM structure should provide good adhesion to a passivation layer of the semiconductor chip and to a metallic bonding pad connected by the via to the final metallization layer. The BLM structure also serves as an effective diffusion barrier between the solder bump and the final metallization layer of the semiconductor chip.
Conventionally, Pb-free C4 bump structures include BLM structures that are centered over vias in the passivation layer of a semiconductor chip. The BLM structures can be formed by: depositing a TiW base layer on the passivation layer and walls of its vias; depositing a Cu seed layer over the TiW base layer; forming a patterned photoresist that forms holes, corresponding to each of the BLM structures, over the Cu seed layer; electroplating a Ni barrier layer on the Cu seed layer in each of the holes; electroplating solder over the electroplated Ni barrier layer in each of the holes; stripping the patterned photoresist; wet etching, with the electroplated solder acting as a mask, the TiW base and Cu seed layers surrounding each of the BLM structures; and reflowing the electroplated solder. In an alternative method of forming Pb-free C4 bump structures, a second Cu layer may be electroplated over the Ni barrier layer in each of the holes, before electroplating the solder.
Pb-free C4 bump structures are also formed by a physical transfer of pre-molded solder bumps to the BLM structures, i.e., a C4 New Process (C4NP). The C4NP process is similar to the conventional Pb-free C4 process, described above, except that following the electroplating of Ni, or alternatively, following the electroplating of a second Cu layer, the patterned photoresist mask is first stripped and the pre-molded solder bumps are then physically transferred to the BLM structures. The TiW base and Cu seed layers, surrounding each of the BLM structures, are subsequently wet etched with the physically transferred solder bumps acting as a mask; and finally, the physically transferred solder bumps are reflowed.
During wet etching of the Cu seed and the TiW base layers surrounding the BLM structures, a chemical undercut of 1-2 μm can occur at the edges of the C4 solder bump structures. Upon subsequent reflow of the C4 solder bump structures during the BEOL processes, there is a thermally driven reaction that occurs between the Sn of the solder and any exposed Cu of the Cu seed layer. This thermal reaction consumes Cu, further undercutting the Cu seed layer, and forms a solid intermetallic mixture, which can comprise Sn, Ni, and Cu within the region of the undercut. The thermal undercut can add an additional undercut of 2-5 μm from the edges of the chemically undercut C4 solder bump structure, resulting in the C4 solder bump structure shown in FIG. 1, which indicates a chemical undercut boundary 108 by the lines with small dashes, a chemical and thermal undercut boundary 106 by the solid lines, and the approximate disposition of the intermetallic by the line with large dashes.
The sum of the chemical and thermal undercuts in the standard electroplated C4 process or the standard physical transfer process for solder bumps typically averages about 4-5 μm from the edges of the C4 solder bump structure. However, variations in the chemical and thermal undercut processes can result in a further additional undercut of 4-5 μm. Therefore, a worst-case maximal sum of chemical and thermal undercuts of the solder bump can range from 5 to 10 μm from the edges of the C4 solder bump structure.
Referring to FIG. 1, mechanical tests reveal that the interface 107 between the TiW base layer 102 and the intermetallic 105, formed within the chemical and thermal undercut 106 region during solder reflow, has a low strength, making it susceptible to shear, when compared to the stronger interfaces of the TiW base layer 102 and the passivation layer 101, the TiW base layer 102 and the Cu seed layer 103, the Cu seed layer 103 and the electroplated Ni layer 104, and the electroplated Ni layer 104 and the intermetallic 105.
Chemical and thermal undercutting of solder bumps can result in chip-level cracking during chip-join cool-down BEOL processes. Recent investigations of the chip-level cracking indicate that during chip-join cool-down, solder bumps disposed between the semiconductor chip and the joined packaging laminate are subject to shearing, which results from the different coefficients of thermal expansion for the chip and the laminate.
There remains a need for a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure and a method of manufacturing a Pb-free C4 with a BLM structure that reduce chip-level cracking during the BEOL processes of chip-join cool-down.